Thin film transistor substrate and method for manufacturing same

ABSTRACT

The present invention relates to a TFT substrate and a manufacture method thereof. The TFT substrate includes a substrate, a plurality of signal lines, a common electrode, and a pixel electrode. The signal lines are arranged on the substrate along two perpendicular directions. One of two signal lines perpendicular to each other includes a plurality of segments. Every two segments closed to each other are arranged on two opposite sides of the other signal line of the two signal lines. The TFT substrate further includes a connecting signal line. The connecting signal line is connected to the two segments of the signal line composing a plurality of segments. The common electrode is arranged in a same layer as the connecting signal line and overlaps the signal line transferring image signals along a direction perpendicular to the substrate.

BACKGROUND

1. Technical Field

The present disclosure relates to thin film transistor (TFT) substrates and methods for manufacturing TFT substrates, and more particularly to a TFT substrate with discontinuity signal lines, wherein the TFT substrate can be used in an in-plane switching (IPS) mode LCDs or in a fringe-field switching (FFS) mode liquid crystal display (LCD).

2. Description of Related Art

LCDs have the advantages of portability, low power consumption, and low radiation, and are widely used in portable electronic devices such as notebooks, personal digital assistants (PDAs), video cameras, and so on. Generally, A TFT substrate of an FFS mode LCD includes a plurality of scan line, a plurality of data line, a plurality of common electrode, a plurality of pixel electrodes, and an insulating layer between the data lines and the pixel electrodes. There is only an insulating layer between the data lines and the pixel electrodes. So the crosstalk disturbances are easy to occur between the data lines and the pixel electrode.

What is needed is a TFT substrate that can overcome the described limitations, and a method for manufacturing such TFT substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of at least one embodiment. In the drawings, like reference numerals designate corresponding parts throughout the various views.

FIG. 1 is a top plan view of part of a TFT substrate of a LCD according to a first embodiment of the present disclosure.

FIG. 2 is a flowchart of a method for manufacturing a TFT substrate, such as, for example, that of FIG. 1, according to a first method embodiment of the present disclosure.

FIGS. 3-7 are cross-sections of successive steps in manufacturing the TFT substrate of FIG. 1 according to the method of FIG. 2.

FIG. 8 is a top plan view of part of a TFT substrate of a LCD according to a second embodiment of the present disclosure.

FIG. 9 is a top plan view of part of a TFT substrate of a LCD according to a third embodiment of the present disclosure.

DETAILED DESCRIPTION

FIG. 1 is a top plan view of part of a TFT substrate 20 of a LCD according to a first embodiment of the present disclosure. The TFT substrate 20 includes a plurality of signal lines 21, a plurality of connection lines 225, a plurality of common electrodes 262, and a plurality of common lines 240.

The signal lines 21 include a plurality of scan lines 210 arranged in a plurality of rows for transmitting a plurality of scanning signals and a plurality of data lines 220 arranged in a plurality of columns for transmitting a plurality of data signals. Each data line 220 is broken to two portions which is disposed at the two side of a scan line 210 and untouched the scan line 210.

The connection line is used to connected the two portions of a data line 220 with two first contact holes 235 respectively. The connection across the scan line 210 perpendicularly and is insolated from the scan line 210. The common electrode 262 lies along the data line 220 in a strip shape. The common electrode 262 is wider than the data line 220. The common line 240 connects the two adjacent common electrodes 262 and parallel to the scan line 210.

The scan lines 241, the data lines 220, and the connection lines 225 define a plurality of pixel areas (unlabeled). Each pixel area includes a TFT switch 230 and a pixel electrode 250. The TTF switch 230 is disposed at the across of the connection line 225 and the scan line 210. Each TFT switch 230 includes a gate electrode 231, a source electrode 232, and a drain electrode 233. The gate electrode 231 is connected to the scan line 210, the source electrode 232 is connected to the connection line 225, and the drain electrode 233 is connected to the pixel electrode 250. The edge of the pixel electrode 250 partly overlaps the common electrode 262 and the scan line 210 respectively.

FIG. 2 is a flowchart of a method for manufacturing a TFT substrate 20, such as, for example, that of FIG. 1, according to a first method embodiment of the present disclosure. The manufacturing method includes, in step S1, forming a plurality of gate electrodes, a plurality of gate lines, and a plurality of un-continuable data lines on a substrate, in step S2, forming a gate insulation layer and a semiconductor pattern in sequentially on the gate electrodes, the gate lines, the data lines and the substrate, in step S3, forming a plurality source electrodes, a plurality of drain electrodes, a plurality of common lines and a plurality of connection lines on the gate insulation layer and the semiconductor pattern, in step S4, forming a passivation layer on the common lines, the connection lines, the gate electrodes, the source electrodes, the drain electrodes, and the gate insulation layer, in step S5, forming a plurality of pixel electrodes on the passivation layer.

In step S1, referring to FIGS. 3, a substrate 270 is provided. A conducting metal film is coated on the substrate 270 to form a first conducting metal layer (not shown). A first photoresist process is provided to the first conducting metal layer to form the gate electrodes 231, the scan lines 210, and the uncontinuable data lines 220. Each two adjacent portions of the data lines 220 are disposed on the two sides of a scan line 210 respectively, and are untouched with the scan line 210.

In step S2, referring to FIG. 4, a gate insulation layer 280 is deposited on the first conducting metal layer and the substrate 270. The material of the gate insulation layer 280 can be the silicon nitride. Then, an a−Si intrinsic layer and a n+Si ohmic contact layer are deposited on the gate insulation layer 280 in sequentially by Chemical Vapor Deposition (CVD). A second photoresist process is provided to form a first contact hole 235 and a semiconductor pattern layer 281. the data lines 220 are exposed by the first contact hole 235.

In step S3, referring to FIG. 5, a conducting metal film is coated on the semiconductor pattern layer 281 and the gate insulation layer 280 to form a second conducting metal layer (not shown). A third photoresist process is provided to the second conducting metal layer to form the source electrode 232, the drain electrode 233, the common electrode 262 and the connection line 225. The common electrode 262 covers the data line 220. The connection line 225 contacts the data line 220 via the first contact hole 235.

In step S4, referring to FIG. 6, a passivation layer 290 is coated on the second conducting metal layer and the gate insulation layer 280. A fourth photoresist process is provided to the passivation layer 290 to form a second contact hole 236.

In step S5, referring to FIG. 7, a transparent conducting layer is coated on the passivation layer 290 by sputtering. The transparent conducting layer is connected the drain electrode 233 via the contact hole 236. A fifth photoresist process is provided to the transparent conducting layer to form a pixel electrode 250 according to the pixel area. The material of the transparent conducting layer can be indium tin oxide (ITO) or indium Zinc oxide (IZO).

FIG. 8 is a top plan view of part of a TFT substrate of a LCD according to a second embodiment of the present disclosure. The structure of the TFT substrate 30 is similar to the TFT substrate 20. The main difference between the TFT substrate 30 and the TFT substrate 20 is as follows: a plurality of data line 320 has a continuation structure. Each scan line 310 is broken to two portions which is disposed at the two side of a data line 320 and untouched the data line 320. Each connection line 325 is disposed between the two adjacent portions of each scan line 310, and contacts the two adjacent portions of each scan line 310 via a first contact hole 335.

FIG. 9 is a top plan view of part of a TFT substrate of a LCD according to a third embodiment of the present disclosure. The structure of the TFT substrate 40 is similar to the TFT substrate 20. The main difference between the TFT substrate 40 and the TFT substrate 20 is as follows: each data line 420 includes a first main body 422 and a plurality of first extension 423. Each connection line includes a second main body 426, two connections 427, and a plurality of second extension 428. The first extensions 423 dispose on the two ends of the first main body 422 respectively, and the second extensions 428 are disposed on the two ends of the second main body 426 respectively. The connection 427 is electrically connected to the first extension 423. The first extension 423 and the second extension 428 are overlapped with the edge of the pixel electrode 450.

Compared with the prior art, the common electrodes are disposed to cover the data lines or the scan lines insolated. So the signal transmitted by the data lines will not disturb the voltage of the pixel electrode. The edges of the pixel electrode can extent to the data line and have a high aperture ratio. 

1. A thin film transistor (TFT) substrate, comprising: a substrate, a plurality of signal lines, a common electrode and a pixel electrode, the signal lines being arranged in a plurality of rows for transmitting a plurality of scanning signals, and a plurality of columns for transmitting a plurality of data signals, the pixel electrode being disposed at ends of the signal lines which are away from the substrate and being isolated with the signal lines, wherein each two of the signal lines that are perpendicular to each other have a signal line broken and untouchedly disposed at two ends of the other signal line, wherein further comprising a connection line disposed between the signal lines and the pixel electrode, the common electrode and the connection line being disposed substantially in a same layer and covering the signal lines in a direction vertical to the substrate.
 2. The TFT substrate of claim 1, wherein the data lines are uncontinuable.
 3. The TFT substrate of a liquid crystal display of claim 2, wherein each data line includes a first main body and a plurality of first extension, the first extensions are disposed on the two ends of the first main body respectively.
 4. The TFT substrate of a liquid crystal display of claim 3, wherein each connection line includes a second main body, two connections, and a plurality of second extension, the second extensions are disposed on the two ends of the second main body respectively, The first extension and the second extension are overlapped with the edge of the pixel electrode.
 5. The TFT substrate of claim 1, wherein the scan lines are uncontinuable.
 6. The TFT substrate of claim 1, wherein the connection line is used to connect the two portions of a signal line with two first contact holes respectively.
 7. The TFT substrate of claim 1, wherein the common electrode is wider than the data line.
 8. A method for manufacturing a thin film transistor (TFT) substrate of claim 10, the method comprising: forming a plurality of gate electrodes, a plurality of gate lines, and a plurality of uncontinuable data lines on a substrate; forming a gate insulation layer and a semiconductor pattern in sequentially on the gate electrodes, the gate lines, the data lines and the substrate; forming a plurality source electrodes, a plurality of drain electrodes, a plurality of common lines and a plurality of connection lines on the gate insulation layer and the semiconductor pattern; forming a passivation layer on the common lines, the connection lines, the gate electrodes, the source electrodes, the drain electrodes, and the gate insulation layer; forming a plurality of pixel electrodes on the passivation layer.
 9. The method of claim 8, wherein the data lines are uncontinuable.
 10. The method of claim 9, wherein each data line includes a first main body and a plurality of first extension, the first extensions are disposed on the two ends of the first main body respectively.
 11. The method of claim 10, wherein each connection line includes a second main body, two connections, and a plurality of second extension, the second extensions are disposed on the two ends of the second main body respectively, The first extension and the second extension are overlapped with the edge of the pixel electrode.
 12. The method of claim 8, wherein the scan lines are uncontinuable.
 13. The method of claim 8, wherein the connection line is used to connect the two portions of a signal line with two first contact holes respectively.
 14. The method of claim 8, wherein the common electrode is wider than the data line. 